1. Field of the Invention
The invention relates generally to methods for forming patterned microelectronic layers within microelectronic products. More particularly, the invention relates to methods for efficiently forming patterned microelectronic layers within microelectronic products.
2. Description of the Related Art
Microelectronic products are formed from substrates over which are formed microelectronic devices. The microelectronic devices in turn are interconnected with patterned conductor layers to form the microelectronic products.
As microelectronic product integration levels have increased and microelectronic device and patterned conductor layer dimensions have decreased, it has become increasingly more difficult to form patterned microelectronic layers with diminished dimensions and enhanced dimensional control.
The present invention is directed towards the foregoing object.
Various methods have been disclosed in the microelectronic product fabrication art for forming patterned layers.
Included but not limited among the methods are those disclosed within: (1) Cher et al., in U.S. Pat. No. 5,453,156 (a plasma etch method employing a fluorine containing etchant gas rather than a chlorine containing etchant gas for forming a patterned polysilicon layer); (2) Linliu et al., in U.S. Pat. No. 6,110,837 (a plasma etch method for forming a patterned hard mask layer of one-half critical dimension); and (3) Kahn et al., in U.S. Pat. No. 6,391,788 (a two-step plasma etch method for forming a patterned layer with enhanced etch efficiency).
The disclosures of each of the foregoing references are incorporated herein fully by reference.
Desirable are additional etch methods for forming patterned layers with diminished dimension and enhanced dimensional control.
The invention is directed towards the foregoing object.
A first object of the invention is to provide a method for forming a patterned layer within a microelectronic product.
A second object of the invention is to provide a method in accord with the first object of the invention, wherein the patterned layer is formed with diminished dimension and enhanced dimensional control.
In accord with the objects of the invention, the invention provides a method for forming a patterned layer within a microelectronic product.
The method first provides a substrate. A blanket target layer is formed over the substrate and a patterned mask layer is formed upon the blanket target layer. The method provides for vertically incompletely etching the blanket target layer while employing a plasma etch method and the patterned mask layer as an etch mask. The vertically incomplete etching provides an incompletely vertically etched blanket target layer and an etch residue layer upon a sidewall of the patterned mask layer. The method further provides for removing the patterned mask layer from the incompletely vertically etched blanket target layer. The method still further provides for further etching the incompletely vertically etched blanket target layer while employing the plasma etch method. The further etching provides a further etched incompletely vertically etched blanket target layer having formed thereupon a laterally increased etch residue layer. Finally, the method provides for further etching the further etched incompletely vertically etched blanket target layer while employing the plasma etch method and the laterally increased etch residue layer as an etch mask to form a patterned target layer.
Thus, the invention employs a single etch method sequentially: (1) with a patterned mask layer formed upon a blanket target layer to form an incompletely vertically etched blanket target layer and an etch residue layer adjoining the patterned mask layer; (2) without the patterned mask layer to form a laterally increased etch residue layer upon a further etched incompletely vertically etched blanket target layer; and (3) with the laterally increased residue layer as a mask to form a patterned target layer from the further etched incompletely vertically etched blanket target layer.
Within the invention, the patterned mask layer may be removed intrinsic to the single plasma etch method or independent of the single plasma etch method.
The invention provides a method for forming a patterned layer of diminished dimension and enhanced dimensional control within a microelectronic product.
The invention realizes the foregoing object within the context of a plasma etch method which provides an etch residue layer upon the sidewall of a patterned mask layer employed for etching a blanket target layer upon which is formed the patterned mask layer. Upon removal of the patterned mask layer, the plasma etch method forms a laterally increased etch residue layer from the etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer.